Verification
:

VERILOG

Title

Description

Duration in hours

1. Introduction

1. What is VLSI? Why VLSI ? Current and future trends in VLSI

2. Introduction to Digital design and Verification

3.Why verification is needed, what is verification, why pre-silicon verification, present trends in verification, future challenges.

3

2. Introduction to HDLs

1. Introduction to Verilog.

2. Verilog for Design and Verilog for Verification.

3. Language constructs and conventions.

4. Basic verilog coding styles and example.

5. Test bench and simulation and result analysis with waveforms.

4

3. Gate Level modeling

1. Gate level modeling with gate primitives

2. Modeling of flops and delays, Tristates, Basic Circuits

3. Exercise on gate level modeling

5

4. Data flow modeling

1. Modeling at Data flow level

2. Assignments statements with delays

3. Assignments to vectors and operators

5

5. Behavioral modeling

1. Behavioral modeling basics constructs

2. Initial and always blocks, functional bifurcation.

3. Loop constructs, wait, if-else, while,foreach,forever

4. Parallel blocks, events, force-release constructs and exercises

10

6. Function, task and UDP's

1. Functions and tasks in verilog

2.UDP's in verilog

3. Exercises

4

7. System tasks and compiler directives

1. Parameters, system tasks and functions

2. compiler directives and hierarchical access.

3. File based tasks and functions.

4

SYSTEM VERILOG

1. Introduction to System Verilog

1. Introduction SV

2. Data Types

3. Data types : Logic.

4. Fixed size arrays, Dynamic Arrays, Queue, Associative arrays.

5. Array methods and user defined data types.

6. Structs and Emun data types.

5

2. Procedural Statements, Function and Tasks

1. Procedural statements

2. Tasks and Functions

3. Arguments passing to tasks and functions

4. Returning from functions and tasks.

5. Local data storage.

5

3. Connecting Testbench with DUT

1. Communication between TB and DUT

2. The Interface construct, Connecting interface and ports

3. Using modports to group the signals and timing considerations

4. Program blocks considerations

5

4. Basics OOP concepts

1. OOP terminology

2. Creating new object,object deallocation, using objects

3. Class methods, defining method outside the class

4. Static v/s global variables, using once class inside another

5. Modifying the object handles, deep copy and shallow copy.

6. Public vs local and Building a TB.

7

5. Interprocess Communication

1. Working with threads.

2. With fork..join, fork..join_any,fork..join_none.

3. Sharing thread, IPC.

4. Evenet, semaphores and mailbox.

5. Building a TB with threads and IPC.

8

6. Projects and Labs

1. A mini project TBD

2. Complete the remaining labs with Q&As.

35


Reference Books & Tutorials:
  1. Verilog : Design through Verilog HDL by T. R. Padmanbhan and B. Bala Tripura Sundari
  2. System Verilog : System Verilog for Verification By Chris Spear and Greg Tumbush 3rd Edition