Physical Design: http://goo.gl/forms/dRHrLZmr74
 

Title

Description

Duration in Hours

1. ASIC Flow

1. Introduction to ASIC flow

2. General Physical Design(PD) flow graph

3. Common PD terminologies and Input/Output tool files 


5


2. Data setup & basic flow

1. Data setup: logical libraries, physical libraries, technology files, extraction model files

2. Defining power connectivity, timing constraints

3. Basics of design planning
4. Power network synthesis

20

3. Design Planning

1. Creating floorplan: Area parameters, macro placements & pin locations

2. Dynamic Behavior: Propagation Delay, Dynamic Power, Static Power, Energy, Delay and Energy-Delay

15


4. Placement

1. Placement setup & checks

2. Placement & optimization based on timing & congestion

3. Incremental optimization, defining path groups, refine placement
4. Scan chain based re-ordering
5. Global route during optimization

20


5. Clock Tree Synthesis(CTS)

1. CTS Gloals: clock-specific targets, generated & gated clocks, SDC latencies, NDR Rules

2. CTS & Timing optimization
3. Enable hold time fixing

20

6. Routing1. Route Steps: Global Route, Track Assignment, Detail Routing
2. Routing optimization, antenna violations, blockages & DFM optimizations
20
7. Chip Finishing
1. Chip finishing flow
2. Wire spreading, filler cells insertion, redundant via insertion
3. Final validation: Parasitics, Netlist, GDSII
10

8. Labs  & Exam

1. Two Theory and 4 Lab sessions for project
2. Written and Mock Interview
10