Digital Phase Locked Loop

Objective :
Implementation of digital phase locked loop in 180nm technology

EDA Tools : Electric, LT Spice

A phase locked loop is a device which generates a clock and synchronizes it with an input signal.The input signal can be data or another clock. The best known application of PLLs is clock recovery in communication. When an signal of a known frequency is being received often a synchronized clock is required to time circuitry which is processing the incoming signal.


Power Supply : 1.8 V

Fmax : 60 MHz

Fmin : 30 MHz