Asynchronous Protocol Converters for Global Communication in SOC

Objective :
Verilog coding and implementation of a converter circuit on Basys II board


EDA Tools : Xilinx ISE , Modelsim

This project proposes two new architecture for a family of asynchronous protocol converters  that translate between two and four- phase protocols, thus facilitating robust system design using efficient  global two- phase communication and local four-phase computation exhibiting  high performance and modest area overhead. The circuit was implemented in Spartan3 Basys II board.



Specifications

Latency : 5ns

Stabilization Time : 9ns

Min. pipelined cycle time: 8ns