8-Bit Successive Approximation Register Analog to Digital Converter for wireless sensor applications

Objective :
8-bit SAR ADC is implemented for low power applications in lower input voltage ranges (0 to 1.2V)

EDA Tools : Cadence, Spice

The present implementation uses 1 MHz clock frequency, 10uA of average current across process corner 1.8V supply voltage. The split array capacitive DAC technique is implemented to decrease the MSB capacitor value. The clocked comparator is implemented to avoid the dc current consumption; the preamplifier is implemented to reduce the offset in the comparator. The implemented preamplifier gain is maintained ~10dB across the corner.  With 1.8V supply it consumes 18uW of power.



Specifications

Resolution : 8 Bit

Power Supply : 1.8 V

Clock Frequency : 1 MHz

Conversion Rate : 100 KSPS

Current Consumption : 10 µA

DNL : ±0.5 LSB

INL : 1 LSB